`timescale 1ns/100ps

module waves_gen();

reg clk_25M;
reg clk_50M;
reg clk_100M;
        
// 100MHz clock signal generator
initial begin
   clk_100M = 1'b0;
   forever #5 clk_100M = ~clk_100M;
end

// 50MHz clock signal generator
initial begin
   clk_50M = 1'b0;
end
always begin
   #10 clk_50M = ~clk_50M;
end

// 25MHz clock signal generator (clock divider)
initial begin
   clk_25M = 1'b0;
end
always begin
   @(posedge clk_50M)
   clk_25M = ~clk_25M;
end

endmodule